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4- 1 hfa3860 11 mbps direct sequence spread spectrum baseband processor the intersil hfa3860 direct sequence (dsss) baseband processor is part of the prism 2.4ghz radio chipset, and contains all the functions necessary for a full or half duplex packet baseband transceiver for applications requiring 11 mbps performance. the hfa3860 has on-board a/ds for analog i and q inputs, for which the hfa3726 if qmodem is recommended. differential phase shift keying modulation schemes dbpsk and dqpsk, with data scrambling capability are available, along with m-ary bi-orthogonal keying to provide a variety of data rates. built-in flexibility allows the hfa3860 to be configured through a general purpose control bus, for a range of applications. a receive signal strength indicator (rssi) monitoring function with on-board 6-bit a/d provides clear channel assessment (cca) to avoid data collisions and optimize network throughput. the hfa3860 is housed in a thin plastic quad flat package (tqfp) suitable for pcmcia board applications. simpli?ed block diagram features ? complete dsss baseband processor ? processing gain . . . . . . . . . . . . . . . . . . . . . . . . . . 3 10.4db ? programmable data rate. . . . . . . . 1, 2, 5.5, and 11 mbps ? ultra small package . . . . . . . . . . . . . . . . . . . . 7 x 7 x 1mm ? single supply operation (44mhz max) . . . . . 2.7v to 3.6v ? modulation methods . . . . . . .dbpsk, dqpsk, and mbok ? supports full or half duplex operations ? on-chip a/d converters for i/q data (3-bit, 22 msps) and rssi (6-bit) ? similar pinout to hfa3824 applications ? systems targeting ieee 802.11 wlan standard ? point-to-point links ? dsss pcmcia wireless transceiver ? spread spectrum wlan rf modems ? tdma packet protocol radios ? part 15 compliant radio links ? portable bar code scanners/pos terminal ? portable pda/notebook computer ? wireless digital audio ? wireless digital video ? pcn/wireless pbx pinout hfa3860 (tqfp) ordering information part no. temp. range ( o c) pkg. type pkg. no. hfa3860iv -40 to 85 48 ld tqfp q48.7x7 HFA3860IV96 -40 to 85 tape and reel ? rssi i in q in i out q out demod. pro- cessor mod. data to network ctrl processor 6-bit a/d 3-bit a/d 3-bit a/d cca spreader de-spreader inter- face 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 rxcl k rxd md_r d rx_pe cca gnd mclk v dd reset antse antse sd e st_ck tx_pe txd txclk t x_rdy r/ w cs v dda gnd i in gnd v dd i out q out test7 test6 test5 v dd gnd test3 test2 test1 test0 test4 q in rssi gnd v refp v refn v dda gnd v dda v dd gnd sdi sclk data sheet july 1998 file number 4347 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 prism? is a registered trademark of intersil corporation. prism logo is a trademark of intersil corporation.
4- 2 table of contents pag e simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 external interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 control port (4 wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 tx port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 rx port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 i/q a/d interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 a/d calibration circuit and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 rssi a/d interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 test port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 power down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 transmitter description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 header/packet description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 scrambler and data encoder description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 spread spectrum modulator description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 clear channel assessment (cca) and energy detect (ed) description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 demodulator description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 acquisition description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pn correlators description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 data demodulation and tracking description (dbpsk and dqpsk modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 data decoder and descrambler description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 data demodulation and tracking description (bmbok and qmbok modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 demodulator performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 a default register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 typical application diagram for additional information on the prism? chip set, call (407) 724-7800 to access intersil answerfax system. when prompted, key in the four-digit document number (file #) of the data sheets you wish to receive. the four-digit ?le numbers are shown in the typical application diagram, and correspond to the appropriate circuit. hfa3860
4- 3 quad if modulator rfpa hfa3925 hfa3726 dsss baseband processor data to mac ctrl hfa3860 hfa3524 0 o /90 o vco a/d a/d mac-phy interface 802.11 vco dual synthesizer hfa3624 up/down converter a/d (file# 4067) (file# 4347) (file# 4062) (file# 4066) (file# 4132) m u x m u x demod mod. de- spread spread q i hfa3424 (note) (file# 4131) typical transceiver application circuit using the hfa3860 note: required for systems targeting 802.11 speci?cations. cca rxi rxq rssi txi txq ? 2 pin descriptions name pin type i/o description v dda (analog) 10, 18, 20 power dc power supply 2.7v - 3.6v (not hardwired together on chip). v dd (digital) 7, 21, 29, 42 power dc power supply 2.7 - 3.6v gnd (analog) 11, 15, 19 ground dc power supply 2.7 - 3.6v, ground (not hardwired together on chip). gnd (digital) 6, 22, 31, 41 ground dc power supply 2.7 - 3.6v, ground. v refn 17 i negative voltage reference for a/ds (i and q) [relative to v refp ] v refp 16 i positive voltage reference for a/ds (i, q and rssi) i in 12 i analog input to the internal 3-bit a/d of the in-phase received data. q in 13 i analog input to the internal 3-bit a/d of the quadrature received data. antsel 26 o the antenna select signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. this is a complement for antsel (pin 27) for differential drive of antenna switches. antsel 27 o the antenna select signal changes state as the receiver switches from antenna to antenna during the acquisition process in the antenna diversity mode. this is a complement for antsel (pin 26) for differential drive of antenna switches. rssi 14 i receive signal strength indicator analog input. hfa3860
4- 4 tx_pe 2 i when active, the transmitter is con?gured to be operational, otherwise the transmitter is in standby mode. tx_pe is an input from the external media access controller (mac) or network processor to the hfa3860. the rising edge of tx_pe will start the internal transmit state machine and the falling edge will initiate shut down of the state machine. tx_pe envelopes the transmit data except for the last bit. the transmitter will continue to run for 3 symbols after tx_pe goes inactive to allow the pa to shut down gracefully. txd 3 i txd is an input, used to transfer mac payload data unit (mpdu) data from the mac or network processor to the hfa3860. the data is received serially with the lsb ?rst. the data is clocked in the hfa3860 at the rising edge of txclk. txclk 4 o txclk is a clock output used to receive the data on the txd from the mac or network processor to the hfa3860, synchronously. transmit data on the txd bus is clocked into the hfa3860 on the rising edge. the clocking edge is also programmable to be on either phase of the clock. the rate of the clock will be dependent upon the data rate that is programmed in the signalling ?eld of the header. tx_rdy 5 o tx_rdy is an output to the external network processor indicating that preamble and header information has been generated and that the hfa3860 is ready to receive the data packet from the network processor over the txd serial bus. the tx_rdy returns to the inactive state when the last chip of the last symbol has been output. cca 32 o clear channel assessment (cca) is an output used to signal that the channel is clear to transmit. the cca algorithm makes its decision as a function of rssi, energy detect (ed), and carrier sense (crs). the cca algorithm and its features are described elsewhere in the data sheet. logic 0 = channel is clear to transmit. logic 1 = channel is not clear to transmit (busy). this polarity is programmable and can be inverted. rxd 35 o rxd is an output to the external network processor transferring demodulated header information and data in a serial format. the data is sent serially with the lsb ?rst. the data is frame aligned with md_rdy. rxclk 36 o rxclk is the bit clock output. this clock is used to transfer header information and payload data through the rxd serial bus to the network processor. this clock re?ects the bit rate in use. rxclk is held to a logic 0 state during the crc16 reception. rxclk becomes active after the sfd has been detected. data should be sampled on the rising edge. this polarity is programmable and can be inverted. md_rdy 34 o md_rdy is an output signal to the network processor, indicating header data and a data packet are ready to be transferred to the processor. md_rdy is an active high signal and it envelopes the data transfer over the rxd serial bus. md_rdy goes active when the sfd is detected and returns to its inactive state when rx_pe goes inactive or an error is detected in the header. rx_pe 33 i when active, the receiver is con?gured to be operational, otherwise the receiver is in standby mode. this is an active high input signal. in standby, rx_pe inactive, all a/d converters are disabled. sd 25 i/o sd is a serial bi-directional data bus which is used to transfer address and data to/from the internal registers. the bit ordering of an 8-bit word is msb ?rst. the ?rst 8 bits during transfers indicate the register address immediately followed by 8 more bits representing the data that needs to be written or read at that register. sclk 24 i sclk is the clock for the sd serial bus.the data on sd is clocked at the rising edge. sclk is an input clock and it is asynchronous to the internal master clock (mclk)the maximum rate of this clock is 11mhz or one half the master clock frequency, whichever is lower. sdi 23 i this pin is not used in the 4 wire interface described in this data sheet. it should not be left ?oating. r/ w8 ir/ w is an input to the hfa3860 used to change the direction of the sd bus when reading or writing data on the sd bus. r/ w also enables the serial shift register used in a read cycle. r/ w must be set up prior to the rising edge of sclk. a high level indicates read while a low level is a write. cs 9 i cs is a chip select for the device to activate the serial control port.the cs doesnt impact any of the other interface ports and signals, i.e., the tx or rx ports and interface signals. this is an active low signal. when inactive sd, sclk, and r/ w become dont care signals. test 7:0 37, 38, 39, 40, 43, 44, 45, 46 o this is a data port that can be programmed to bring out internal signals or data for monitoring. these bits are primarily reserved by the manufacturer for testing. a further description of the test port is given at the appropriate section of this data sheet. pin descriptions (continued) name pin type i/o description hfa3860
4- 5 external interfaces there are three primary digital interface ports for the hfa3860 that are used for con?guration and during normal operation of the device as shown in figure 1. these ports are: ? the control port , which is used to con?gure, write and/or read the status of the internal hfa3860 registers. ? the tx port , which is used to accept the data that needs to be transmitted from the network processor. ? the rx port , which is used to output the received demodulated data to the network processor. in addition to these primary digital interfaces the device includes a byte wide parallel test port which can be con?gured to output various internal signals and/or data. the device can also be set into various power consumption modes by external control. the hfa3860 contains three analog to digital (a/d) converters. the analog interfaces to the hfa3860 include, the in phase (i) and quadrature (q) data component inputs, and the rf signal strength indicator input. a reference voltage divider is also required external to the device. control port (4 wire) the serial control port is used to serially write and read data to/from the device. this serial port can operate up to a 11mhz rate or 1/2 the maximum master clock rate of the device, mclk (whichever is lower). mclk must be running during programming. this port is used to program and to read all internal registers. the ?rst 8 bits always represent the address followed immediately by the 8 data bits for that register. the two lsbs of address are dont care, but reserved for future expansion. the serial transfers are accomplished through the serial data pin (sd). sd is a bidirectional serial data bus. chip select ( cs), and read/ wr ite (r/ w) are also required as handshake signals for this port. the clock used in conjunction with the address and data on sd is sclk. this clock is provided by the external source and it is an input to the hfa3860. the timing relationships of these signals are illustrated in figures 2 and 3. r/ w is high when data is to be read, and low when it is to be written. cs is an asynchronous reset to the state machine. cs must be active (low) during the entire data transfer cycle. cs selects the serial control port device only. the serial control port operates asynchronously from the tx and rx ports and it can accomplish data transfers independent of the activity at the other digital or analog ports. the hfa3860 has 32 internal registers that can be accessed through the control port. these registers are listed in the configuration and control internal register table. table 1 lists the configuration register number, a brief name describing the register, and the hex address to access each of the registers. the type indicates whether the corresponding register is read only (r) or read/write (r/w). some registers are two bytes wide as indicated on the table (high and low bytes). see tech brief #360 on timing issues between the serial clock (sclk) and the chip master clock (mclk). test_ck 1 o this is the clock that is used in conjunction with the data that is being output from the test bus (test 0-7). reset 28 i master reset for device. when active tx and rx functions are disabled. if reset is kept low the hfa3860 goes into the power standby mode. reset does not alter any of the configuration register values nor does it preset any of the registers into default values. device requires programming upon power-up. after reset is de-activated, rx_pe must be activated for at least 2 mclks before rx and tx functions are restored. mclk 30 i master clock for device. the nominal frequency of this clock is 44mhz. this is used internally to generate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks. i out 48 o tx spread baseband i digital output data. data is output at the chip rate. q out 47 o tx spread baseband q digital output data. data is output at the chip rate. note: total of 48 pins; all pins are used. pin descriptions (continued) name pin type i/o description txd txclk tx_rdy rxd rxc md_rdy c s sd sclk r/ w sdi i (analog) q (analog) rssi (analog) v refn v refp tx_pe rx_pe reset test tx_port rx_port control_port analog inputs a/d reference power down signals test port 8 hfa3860 figure 1. external interface antsel hfa3860
4- 6 notes: 1. the hfa3860 always uses the rising edge of sclk. sd, r/ w and cs hold times allow the controller to use either the rising or falling edge. 2. this port operates essentially the same as the hfa 3824 with the exception that the as signal of the 3824 is not required. figure 2. control port read timing figure 3. control port write timing 7654321076543210 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 sclk sd cs r/ w lsb data out msb msb address in first address bit first databit out 7654321076543210 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 sclk sd cs r/ w lsb data in msb msb address in table 1. configuration and control internal register list configuration register name type register address hex cr0 part/version code r 00 cr1 i/o polarity r/w 04 cr2 tx and rx control r/w 08 cr3 a/d_cal_pos register r/w 0c cr4 a/d_cal_neg register r/w 10 cr5 cca antenna control r/w 14 cr6 preamble length r/w 18 cr7 scramble_tap (rx and tx) r/w 1c cr8 rx_sq1_ acq (high) threshold r/w 20 cr9 rx-sq1_ acq (low) threshold r/w 24 cr10 rx_sq2_ acq (high) threshold r/w 28 cr11 rx-sq2_ acq (low) threshold r/w 2c cr12 sq1 cca thresh (high) r/w 30 cr13 sq1 cca thresh (low) r/w 34 cr14 ed or rssi thresh r/w 38 cr15 sfd timer r/w 3c cr16 signal field (bpsk - 11 chip sequence) r/w 40 cr17 signal field (qpsk - 11 chip sequence) r/w 44 hfa3860
4- 7 tx port the transmit data port accepts the data that needs to be transmitted serially from an external data source. the data is modulated and transmitted as soon as it is received from the external data source. the serial data is input to the hfa3860 through txd using the next rising edge of txclk to clock it in the hfa3860. txclk is an output from the hfa3860. a timing scenario of the transmit signal handshakes and sequence is shown on timing diagram figure 4. the external processor initiates the transmit sequence by asserting tx_pe. tx_pe envelopes the transmit data packet on txd. the hfa3860 responds by generating a preamble and header. before the last bit of the header is sent, the hfa3860 begins generating txclk to input the serial data on txd. txclk will run until tx_pe goes back to its inactive state indicating the end of the data packet. the user needs to hold tx_pe high for as many clocks as there bits to transmit. for the higher data rates, this will be in multiples of the number of bits per symbol. the hfa3860 will continue to output modulated signal for 2 m s after the last data bit is output, to supply bits to flush the modulation path. tx_pe must be held until the last data bit is sampled. the minimum tx_pe inactive pulse required to restart the preamble and header generation is 2.22 m s and to reset the modulator is 4.22 m s. the hfa3860 internally generates the preamble and header information from information supplied via the control registers. the external source needs to provide only the data portion of the packet and set the control registers. the timing diagram of this process is illustrated on figure 4. assertion of tx_pe will initialize the generation of the preamble and header. tx_rdy, which is an output from the hfa3860, is used to indicate to the external processor that the preamble has been generated and the device is ready to receive the data packet (mpdu) to be transmitted from the external processor. signals tx_rdy, tx_pe and txclk can be set individually, by programming configuration register (cr) 1, as either active high or active low signals. the transmit port is completely independent from the operation of the other interface ports including the rx port, therefore supporting a full duplex mode. cr18 signal field (bpsk - mod. walsh sequence) r/w 48 cr19 signal field (qpsk - mod. walsh sequence) r/w 4c cr20 tx signal field r/w 50 cr21 tx service field r/w 54 cr22 tx length field (high) r/w 58 cr23 tx length field (low) r/w 5c cr24 rx status r 60 cr25 rx service field status r 64 cr26 rx length field status (high) r 68 cr27 rx length field status (low) r 6c cr28 test bus address r/w 70 cr29 test bus monitor r 74 cr30 test register 1, must load 00h r/w 78 cr31 test register 2, must load 02h r/w 7c table 1. configuration and control internal register list (continued) configuration register name type register address hex hfa3860
4- 8 rx port the timing diagram figure 5 illustrates the relationships between the various signals of the rx port. the receive data port serially outputs the demodulated data from rxd. the data is output as soon as it is demodulated by the hfa3860. rx_pe must be at its active state throughout the receive operation. when rx_pe is inactive the device's receive functions, including acquisition, will be in a stand by mode. rxclk is an output from the hfa3860 and is the clock for the serial demodulated data on rxd. md_rdy is an output from the hfa3860 and it may be set to go active after sfd or crc fields. note that rxclk becomes active after the start frame delimiter (sfd) to clock out the signal, service, and length fields, then goes inactive during the header crc field. rxclk becomes active again for the mpdu. md_rdy returns to its inactive state after rx_pe is deactivated by the external controller, or if a header error is detected. a header error is either a failure of the crc check, or the failure of the received signal field to match one of the 4 programmed signal fields. for either type of header error, the hfa3860 will reset itself after reception of the crc field. if md_rdy had been set to go active after crc, it will remain low. md_rdy and rxclk can be configured through cr 1, bit 6-7 to be active low, or active high. the receive port is completely independent from the operation of the other interface ports including the tx port, supporting therefore a full duplex mode. i/q a/d interface the prism baseband processor chip (hfa3860) includes two 3-bit analog to digital converters (a/ds) that sample the analog input from the if down converter. the i/q a/d clock, samples at twice the chip rate. the nominal sampling rate is 22mhz. the interface speci?cations for the i and q a/ds are listed in table 2. lsb data packet msb deasserted when last txclk tx_pe txd tx_rdy note: preamble/header and data is transmitted lsb ?rst. txd shown generated from rising edge of txclk. figure 4. tx port timing first data bit sampled last data bit sampled chip of mpdu clears mod path of 3860 rxclk rx_pe md_rdy rxd processing lsb data msb preamble/header note: md_rdy active after crc16. see detailed timing diagrams on page 35. figure 5. rx port timing header fields mpdu data hfa3860
4- 9 the voltages applied to pin 16,v refp and pin 17, v refn set the references for the internal i and q a/d converters. in addition, v refp is also used to set the rssi a/d converter reference. for a nominal i/q input of 500mv p-p , the suggested v refp voltage is 1.75v, and the suggested v refn is 0.93v. v refn should never be less than 0.25v. figure 6 illustrates the suggested interface con?guration for the a/ds and the reference circuits since these a/ds are intended to sample ac voltages, their inputs are biased internally and they should be capacitively coupled. the hpf corner frequency in the baseband receive path should be less than 1khz. . the a/d section includes a compensation (calibration) circuit that automatically adjusts for temperature and component variations of the rf and if strips. the variations in gain of limiters, agc circuits, ?lters etc. can be compensated for up to 4db. without the compensation circuit, the a/ds could see a loss of up to 1.5 bits of the 3 bits of quantization. the a/d calibration circuit adjusts the a/d reference voltages to maintain optimum quantization of the if input over this variation range. it works on the principle of setting the reference to insure that the signal is at full scale (saturation) a certain percentage of the time. note that this is not an agc and it will compensate only for slow variations in signal levels (several seconds). the procedure for setting the a/d references to accommodate various input signal voltage levels is to set the reference voltages so that the a/d calibration circuit is operating at half scale with the nominal input. this leaves the maximum amount of adjustment room for circuit tolerances. a/d calibration circuit and registers the a/d compensation or calibration circuit is designed to optimize a/d performance for the i and q inputs by maintaining the full 3-bit resolution of the outputs. there are two registers (cr 3 ad_cal_pos and cr 4 ad_cal_neg) that set the parameters for the internal i and q a/d calibration circuit. both i and q a/d outputs are monitored by the a/d calibration circuit as shown in figure 7 and if either has a full scale value, a 24-bit accumulator is incremented as de?ned by parameter ad_cal_pos. if neither has a full scale value, the accumulator is decremented as de?ned by parameter ad_cal_neg. the output of this accumulator is used to drive d/a converters that adjust the a/ds references. loop gain reduction is accomplished by using only the 5 msbs out of the 24 bits. the compensation adjustment is updated at a 1khz rate. the a/d calibration circuit is only intended to remove slow component variations. for best performance, the optimum probability that either the i or q a/d converter is at the saturation level was determined to be 33%. the probability p is set by the formula: p(ad_cal_pos)+(1-p)(ad_cal_neg) = 0. one solution to this formula for p = 1/3 is: ad_cal_pos= 2 ad_cal_neg = -1 this also sets the levels so that operation with either noise or signal is approximately the same. it is assumed that the rf and if sections of the receiver have enough gain to cause limiting on thermal noise. this will keep the levels at the a/d approximately the same regardless of whether signal is present or not. the a/d calibration is normally set to work only while the receiver is tracking, but it can be set to operate all the time the receiver is on or it can be turned off and held at mid scale. the a/d calibration circuit operation can be de?ned through cr 2, bits 3 and 4. table 3 illustrates the possible con?gurations. the a/d cal function should initially be programmed for mid scale operation to preset it, then programmed for either tracking mode. this initializes the part for most rapid settling on the appropriate values. table 2. i, q, a/d specifications parameter min typ max full scale input voltage (v p-p ) 0.25 0.50 1.0 input bandwidth (-0.5db) - 20mhz - input capacitance (pf) - 5 - input impedance (dc) 5k w -- fs (sampling frequency) - 22 22mhz 0.15 m f 0.15 m f 3.9k 8.2k 9.1k i q 2v i in q in v refp v refn hfa3860 0.01 m f 0.01 m f figure 6. interfaces table 3. a/d calibration cr 2 bit 4 cr 2 bit 3 a/d calibration circuit configuration 0 0 off, reference set at mid scale. 0 1 off, reference set at mid scale. 1 0 a/d_cal while tracking only. 1 1 a/d_cal while rx_pe active. hfa3860
4- 10 rssi a/d interface the receive signal strength indication (rssi) analog signal is input to a 6-bit a/d, indicating 64 discrete levels of received signal strength. this a/d measures a dc voltage, so its input must be dc coupled. pin 16 (v refp ) sets the reference for the rssi a/d converter. v refp is common for the i and q and rssi a/ds. the rssi signal is used as an input to the clear channel assessment (cca) algorithm of the hfa3860. the rssi a/d output is stored in an 6-bit register available via the test bus and the test bus monitor register. cca is further described on page 15. the interface speci?cations for the rssi a/d are listed in table 4 below (v refp = 1.75v). test port the hfa3860 provides the capability to access a number of internal signals and/or data through the test port, pins test 7:0. in addition pin 1 (test_ck) is an output that can be used in conjunction with the data coming from the test port outputs. the test port is programmable through con?guration register (cr28). any signal on the test port can also be read from con?guration register (cr29) via the serial control port. there are 32 modes assigned to the prism test port. some are only applicable to factory test (table 5). d/a d/a select +fs or -fs compare +fs or -fs compare accumulator (25-bit) test reg mode 1 (7) reg a/dcal test reg mode 25 (8:0) a/d_cal_accum (1/4 db per lsb) a/d_cal_ck (approx 1khz) a/d a/d rx_i_in rx_q_in a/d_ck / 3 / 3 a/d_cal_pos a/d_cal_neg / 8 / 8 to rssi a/d v refn v refp analog biases 8 5 msbs 5 to correlator figure 7. a/d cal circuit table 4. rssi a/d specifications parameter min typ max full scale input voltage - - 1.15 input bandwidth (0.5db) 1mhz - - input capacitance - 7pf - input impedance (dc) 1m - - table 5. test modes mode description test_clk test (7:0) 0 quiet test bus 0 00 1 rx acquisition monitor initial detect a/dcal, crs, ed, track, sfd detect, signal field ready, length field ready, header crc valid 2 tx field monitor iqmark a/dcal, txpe internal, preamble start, sfd start, signal field start, length field start, crc start, mpdu start 3 rssi monitor rssi pulse cse latched, cse, rssi out (5:0) 4 sq1 monitor pulse after sq is valid sq1 (7:0) 5 sq2 monitor pulse after sq is valid sq2 (7:0) 6 correlator lo rate sample clk correlator magnitude (7:0) 7 freq test lo rate subsample clk frequency register (18:11) 8 phase test lo rate subsample clk phase register (7:0) 9 nco test lo rate subsample clk nco register (15:8) hfa3860
4- 11 10 (0ah) bit sync accum lo rate sample clk bit sync accum (7:0) 11 reserved reserved factory test only 12 a/d cal test mode a/d cal clk a/dcal, ed, a/dcal disable, adcal (4:0) 13 correlator i high rate sample clk correlator i (8:1) 14 correlator q high rate sample clk correlator q (8:1) 15 chip error accumulator 0 chip error accum (14:7) 16 nco test hi rate sample clk nco accum (19:12) 17 freq test hi rate sample clk lag accum (18:11) 18 carrier phase error hi rate sample clk carrier phase error (6,6:0) 19 reserved sample clk factory test only 20 reserved sample clk factory test only 21 i_a/d, q_a/d sample clk 0,0,i_a/d (2:0),q_a/d (2:0) 22 reserved reserved factory test only 23 reserved reserved factory test only 24 reserved reserved factory test only 25 a/d cal accum lo a/d cal accum (8) a/d cal accum (7:0) 26 a/d cal accum hi a/d cal accum (17) a/d cal accum (16:9) 27 freq accum lo freq accum (15) freq accum (14:7) 28 reserved reserved factory test only 29 sq2 monitor hi pulse after sq valid sq2 (15:8) 30-31 reserved reserved factory test only table 5. test modes (continued) mode description test_clk test (7:0) table 6. power down modes mode rx_pe tx_pe reset at 44mhz device state sleep inactive inactive active 4ma both transmit and receive functions disabled. device in sleep mode. control interface is still active. register values are maintained. device will return to its active state within 10 m s plus settling time of ac coupling capacitors (about 5ms). standby inactive inactive inactive 11ma both transmit and receive operations disabled. device will resume its operational state within 1 m s of rx_pe or tx_pe going active. tx inactive active inactive 15ma receiver operations disabled. receiver will return in its operational state within 1 m s of rx_pe going active. rx active inactive inactive 24ma transmitter operations disabled. transmitter will return to its operational state within 2 mclks of tx_pe going active. no clock i cc standby active 300 m a all inputs at v cc or gnd. hfa3860
4- 12 de?nitions ed. energy detect, indicates that the rssi value exceeds its programmed threshold. crs. carrier sense, indicates that a signal has been acquired (pn acquisition). txclk. transmit clock. track. indicates start of tracking and start of sfd time-out. sfd detect. variable time after track starts. signal field ready. ~ 8 m s after sfd detect. length field ready. ~ 32 m s after sfd detect. header crc valid. ~ 48 m s after sfd detect. dclk. data bit clock. frqreg. contents of the nco frequency register. phasereg. phase of signal after carrier loop correction. nco phaseaccumreg. contents of the nco phase accu- mulation register. sq1. signal quality measure #1. contents of the bit sync accumulator. eight msbs of most recent 16-bit stored value. sq2. signal quality measure #2. signal phase variance after removal of data, eight msbs of most recent 16-bit stored value. sample clk. receive clock (rx sample clock). nominally 22mhz. subsample clk. lo rate symbol clock. nominally 1mhz. bitsyncaccum. real time monitor of the bit synchronization accumulator contents, mantissa only. a/d_cal_ck. clock for applying a/d calibration corrections. a/dcal. 5-bit value that drives the d/a adjusting the a/d reference. power down modes the power consumption modes of the hfa3860 are controlled by the following control signals. receiver power enable (rx_pe, pin 33), which disables the receiver when inactive. transmitter power enable (tx_pe, pin 2), which disables the transmitter when inactive. reset ( reset, pin 28), which puts the receiver in a sleep mode. the power down mode where, both reset and rx_pe are used is the lowest possible power consumption mode for the receiver. exiting this mode requires a maximum of 10 m s before the device is back at its operational mode. it also requires that rx_pe be activated brie?y to clock in the change of state. the contents of the con?guration registers are not effected by any of the power down modes. the external processor does have access and can modify any of the crs during the power down modes. no recon?guration is required when returning to operational modes. table 6 describes the power down modes available for the hfa3860 (v cc = 3.3v). the table values assume that all other inputs to the part (mclk, sclk, etc.) continue to run except as noted. transmitter description the hfa3860 transmitter is designed as a direct sequence spread spectrum phase shift keying (dsss psk) modulator. it can handle data rates of up to 11 mbps (refer to ac and dc speci?cations). the various modes of the modulator are differential binary phase shift keying (dbpsk), differential quaternary phase shift keying (dqpsk), binary m-ary bi-orthogonal keying (bmbok), and quaternary m-ary bi-orthogonal keying (qmbok). these implement data rates of 1, 2, 5.5 and 11 mbps as shown in figure 8. the major functional blocks of the transmitter include a network processor interface, dpsk modulator, high rate modulator, a data scrambler and a spreader, as shown on figure 8. a description of (m-ary) bi-orthogonal keying can be found in chapter 5 of: telecommunications system engineering, by lindsey and simon, prentis hall publishing. the preamble and header are always transmitted as dbpsk waveforms while the data packets can be con?gured to be either dbpsk, dqpsk, bmbok, or qmbok. the preamble is used by the receiver to achieve initial pn synchronization while the header includes the necessary data ?elds of the communications protocol to establish the physical layer link. the transmitter generates the synchronization preamble and header and knows when to make the dbpsk to dqpsk or b/qmbok switchover, as required. for the psk modes, the transmitter accepts data from the external source, scrambles it, differentially encodes it as either dbpsk or dqpsk, and mixes it with the bpsk pn spreading. the baseband digital signals are then output to the external if modulator. for the mbok modes, the transmitter inputs the data and forms it into nibbles (4 bits). at 5.5 mbps, it selects one of 8 spread sequences from a table of sequences with 3 of those bits and then picks the true or inverted version of that sequence with the remaining bit. thus, there are 16 possible spread sequences to send, but only one is sent. this sequence is then modulated on both the i and q outputs. the phase of the last bit of the header is used as an absolute phase reference for the data portion of the packet. at 11 mbps, two nibbles are used, and each one is used as above independently. one of the resulting sequences is modulated on the i channel and the other on the q channel output. with 16 possible sequences on i and another 16 independently on q, the total possible number of combinations is 256. of these only one is sent. hfa3860
4- 13 table 7 shows examples of the bit rates and the symbol rates and figure 8 shows the modulation schemes. the modulator is completely independent from the demodulator, allowing the prism baseband processor to be used in full duplex operation. header/packet description the hfa3860 is designed to handle continuous or packetized direct sequence spread spectrum (dsss) data transmissions. the hfa3860 generates its own preamble and header information. the device uses a synchronization preamble of up to 256 symbols, and a header that includes ?ve ?elds. the preamble is all 1's (before entering the scrambler). the actual transmitted pattern of the preamble will be randomized by the scrambler. the preamble is always transmitted as a dbpsk waveform. the ?ve ?elds for the header shown in figure 9 are: start frame delimiter (sfd) field (16 bits) - this ?eld carries the synchronization to establish the link frame timing. the hfa3860 will not declare a valid data packet, even if it pn acquires, unless it detects the sfd. the hfa3860 receiver is programmed to time out searching for the sfd via cr15. the timer starts counting the moment that initial pn synchronization has been established from the preamble. signal field (8 bits) - this ?eld indicates what data rate the data packet that follows the header will be. the hfa3860 receiver looks at the signal ?eld to determine whether it needs to switch from dbpsk demodulation into dqpsk or b/qmbok demodulation at the end of the always dbpsk preamble and header ?elds. service field (8 bits) - this ?eld is currently unassigned and can be utilized as required by the user. set to 00h for table 7. bit rate table examples for mclk = 44mhz data modulation a/d sample clock (mhz) tx setup cr 20 bits 1, 0 rx status cr 24 bits 7, 6 data rate (mbps) symbol rate (msps) dbpsk 44 00 00 1 1 dqpsk 44 01 01 2 1 bmbok 44 10 10 5.5 1.375 qmbok 44 11 11 11 1.375 802.11 dsss bpsk 802.11 dsss qpsk 5.5 mb/s bmbok 11 mb/s qmbok 1 mb/s barker 2 mb/s barker data iout qout chip rate 1 bit encoded to one of 2 code words 2 bits encoded 4 code words 4 bits encoded to one of 16 modified walsh code words 8 bits encoded to 256 modified walsh code words symbol rate i vs q 11 mc/s 11 mc/s 11 mc/s 11 mc/s 1 ms/s 1 ms/s 1.375 ms/s 1.375 ms/s 11 chips 11 chips 8 chips 8 chips modified modified (true/inverse) to one of figure 8. modulation modes walsh functions walsh functions one of hfa3860
4- 14 compliance with ieee 802.11. length field (16 bits) - this ?eld indicates the number of microseconds it will take to transmit the payload data (mpdu). the external controller will check the length ?eld in determining when it needs to de-assert the rx_pe. ccitt - crc 16 field (16 bits)- this ?eld includes the 16- bit ccitt - crc 16 calculation of the ?ve header ?elds. this value is compared with the ccitt - crc 16 code calculated at the receiver. the hfa3860 receiver will indicate a ccitt - crc 16 error via cr24 bit 2 and will lower md_rdy if there is an error. the crc or cyclic redundancy check is a ccitt crc-16 fcs (frame check sequence). it is the ones compliment of the remainder generated by the modulo 2 division of the protected bits by the polynomial: x 16 + x 12 + x 5 + 1 the protected bits are processed in transmit order. all crc calculations are made prior to data scrambling. a shift register with two taps is used for the calculation. it is preset to all ones and then the protected ?elds are shifted through the register. the output is then complemented and the residual shifted out msb ?rst. the following configuration registers (cr) are used to program the preamble/header functions, more programming details about these registers can be found in the control registers section of this document: cr 6 defines the preamble length in symbols. the 802.11 protocol requires a setting of 128d = 80h. cr 15 - defines the length of time that the demodulator searches for the sfd before returning to acquisition. cr 16. the contents of this register define dbpsk modulation. if cr 20 bits 1 and 0 are set to indicate dbpsk modulation then the contents of this register are transmitted in the signal field of the header. cr 17. the contents of this register define dqpsk modulation. if cr 20 bits 1 and 0 are set to indicate dqpsk modulation then the contents of this register are transmitted in the signal field of the header. cr 18. the contents of this register define bmbok modula- tion. if cr 20 bits 1 and 0 are set to indicate bmbok modula- tion then the contents of this register are transmitted in the signal field of the header. cr 19. the contents of this register define qmbok modula- tion. if cr 20 bits 1 and 0 are set to indicate qmbok modula- tion then the contents of this register are transmitted in the signal field of the header. cr 20. the last two bits of the register indicate what modula- tion is to be used for the data portion of the packet. cr 21. the value to be used in the service field. cr 22, 23. defines the value of the transmit data length field. this value includes all symbols following the last header field symbol and is in microseconds required to transmit the data at the chosen data rate. the packet consists of the preamble, header and mac protocol data unit (mpdu). the data is transmitted exactly as received from the control processor. some dummy bits will be appended to the end of the packet to insure an orderly shutdown of the transmitter. this prevents spectrum splatter. at the end of a packet, the external controller is expected to de-assert the tx_pe line to shut the transmitter down. scrambler and data encoder description the modulator has a data scrambler that implements the scrambling algorithm speci?ed in the ieee 802.11 standard. this scrambler is used for the preamble, header, and data in all modes. the data scrambler is a self synchronizing circuit. it consist of a 7-bit shift register with feedback from speci?ed taps of the register, as programmed through con?guration register cr 7. both transmitter and receiver use the same scrambling algorithm. the scrambler can be disabled by setting the taps to 0. scrambling is done by a polynomial division using a prescribed polynomial as shown in figure 10. a shift register holds the last quotient and the output is the exclusive-or of the data and the sum of taps in the shift register. the taps are programmable. the transmit scrambler seed is hex 6c and the taps are set with cr 7. for the 1 mbps dbpsk data rates and for the header in all rates, the data coder implements the desired dbpsk coding by preamble (sync) 128 bits sfd 16 bits signal field 8 bits service field 8 bits length field 16 bits crc16 16 bits header preamble figure 9. 802.11 preamble/header figure 10. scrambling process z -1 z -2 z -3 z -4 z -5 z -6 z -7 xor xor serial data input serial data output hfa3860
4- 15 differential encoding the serial data from the scrambler and driving both the i and q output channels together. for the 2 mbps dqpsk data rate, the data coder implements the desired coding as shown in the dqpsk data encoder table (table 8). this coding scheme results from differential coding of dibits (2 bits). vector rotation is counterclockwise although b its 5 and 6 of con?guration register cr2 can be used to reverse the rotation sense of the tx or rx signal if needed. for data modulation in the mbok modes, the data is formed into nibbles (4 bits). for binary mbok modulation (5.5 mbps) one nibble is used per symbol and for quaternary mbok (11 mbps), two are used. the data is not differentially encoded, just scrambled, in these modes. spread spectrum modulator description the modulator is designed to generate dbpsk, dqpsk, bmbok, and qmbok spread spectrum signals. the modulator is capable of automatically switching its rate where the preamble and header are dbpsk modulated, and the data is differentially modulated. the modulator can support data rates of 1, 2, 5.5 and 11 mbps. the programming details to set up the modulator are given at the introductory paragraph of this section. the hfa3860 utilizes quadraphase (i/q) modulation at baseband for all modulation modes. in the 1 mbps dbpsk mode, the i and q channels are connected together and driven with the output of the scrambler and differential encoder. the i and q channels are then both multiplied with the 11-bit barker word at the spread rate. the i and q signals go to the quadrature upconverter (hfa 3724) to be modulated onto a carrier. thus, the spreading and data modulation are bpsk modulated onto the carrier. for the 2 mbps dqpsk mode, the serial data is formed into dibits or bit pairs in the differential encoder as detailed above. one of the bits in a dibit goes to the i channel and the other to the q channel. the i and q channels are then both multiplied with the 11-bit barker word at the spread rate. this forms qpsk modulation at the symbol rate with bpsk modulation at the spread rate. for the 5.5 mbps binary m-ary bi-orthogonal keying (bmbok) mode, the output of the scrambler is partitioned into nibbles of sign-magnitude (4 bits lsb first). the magnitude bits are used to select 1 of 8 eight bit modified walsh functions. the walsh functions are modified by adding hex 03 to all members of a walsh function set to insure that there is no all 0 member as shown in table 9. the selected function is then xord with the sign bit and connected to both i and q outputs. the modified walsh functions are clocked out at the spread rate (nominally 11 mcps). the symbol rate is 1/8th of this rate. the differential encoder output of the last bit of the header crc is the phase reference for the high rate data. this reference is xord with the i and q data before the output. this allows the demodulator to compensate for phase ambiguity without differential encoding the high rate data. for the 11 mbps qmbok mode, the output of the scrambler is partitioned into two nibbles. each nibble is used as above to select a modi?ed walsh function and set its sign. the ?rst of these modi?ed walsh spreading functions goes to the q channel and the second to the i channel. they are then both xord with the phase reference developed from the last bit of the header crc from the differential encoder. clear channel assessment (cca) and energy detect (ed) description the clear channel assessment (cca) circuit implements the carrier sense portion of a carrier sense multiple access (csma) networking scheme. the clear channel assessment (cca) monitors the environment to determine when it is feasible to transmit. the result of the cca algorithm is available 16 m s after rx_pe goes high through output pin 32 of the device. the cca circuit in the hfa3860 can be programmed to be a function of rssi (energy detected on the channel), carrier detection, or both. the cca output can be ignored, allowing transmissions independent of any channel conditions. the cca in combination with the visibility of the various internal parameters (i.e., energy detection measurement results), can assist an external processor in executing algorithms that can adapt to the environment. these algorithms can increase network throughput by minimizing collisions and reducing transmissions liable to errors. table 8. dqpsk data encoder phase shift dibit pattern (d0, d1) d0 is first in time 000 +90 01 +180 11 -90 10 table 9. modified walsh functions mag mwal data pattern lsb.......msb 0 03 11000000 1 0c 00110000 2 30 00001100 3 3f 11111100 4 56 01101010 5 59 10011010 6 65 10100110 7 6a 01010110 hfa3860
4- 16 there are two measures that are used in the cca assessment. the receive signal strength (rssi) which measures the energy at the antenna and carrier sense early (cse). both indicators are normally used since interference can trigger the signal strength indication, but it might not trigger the carrier sense. the carrier sense, however, becomes active only when a spread signal with the proper pn code has been detected, so it may not be adequate in itself. the cca compares these measures to thresholds at the end of each antenna dwell following rx_pe going active. the cca, by design, indicates busy from the time rx_pe goes high until the cca assessment is made. cca should be sampled 16 m s after raising rx_pe. the receive signal strength indication (rssi) measurement is an analog input to the hfa3860 from the successive if stage of the radio. the rssi a/d converts it within the baseband processor and it compares it to a programmable threshold. this threshold is normally set to between -70 and -80dbm. a mac controlled calibration procedure can be used to optimize this threshold. this measure is used in the clear channel assessment logic. the cse (carrier sense early) is a signal that goes active when sq1 (after an antenna dwell) has been satisfied. it is called early, since it is indicated before the carrier sense used for acquisition. it is calculated on the basis of the integrated energy in the correlator output over a block of 15 symbols. thus, the cca is valid after 16 m s has transpired from the time rx_pe was raised. the configuration registers effecting the cca algorithm operation are summarized below (more programming details on these registers can be found under the control registers section of this document). the cca output from pin 32 of the device can be defined as active high or active low through cr 1 (bit 5). the rssi threshold is set through cr14. if the actual rssi value from the a/d exceeds this threshold then ed becomes active. the instantaneous rssi value can be monitored by the external network processor by reading the test bus in mode 3. it only measures the signal 16 m s after the receiver becomes active. the programmable threshold on the cse measurement is set through cr12 and cr13. more details on sq1 are included in the receiver section of this document. in a typical single antenna system cca will be monitored to determine when the channel is clear. once the channel is detected busy, cca should be checked periodically to determine if the channel becomes clear. cca is stable to allow asynchronous sampling or even falling edge detection of cca. once md_rdy goes active, cca is then ignored for the remainder of the message. failure to monitor cca until md_rdy goes active (or use of a time-out circuit) could result in a stalled system as it is possible for the channel to be busy and then become clear without an md_rdy occurring. a dual antenna system has the added complexity that cca will potentially toggle between active and inactive as each antenna is checked. the user must avoid mistaking the inactive cca signal as an indication the channel is clear. a time-out circuit that begins with the ?rst busy channel indication could be used. alternatively cca could be monitored for a clear channel indication for 2 successive antenna dwells which would show the channel clear on both antennas. time alignment of cca monitoring with the receivers 16 m s antenna dwells would required. once the receiver has acquired, cca should be monitored for loss of signal until md_rdy goes active. cr5 selects the starting antenna used when rxpe is brought active. cse is updated at the end of each antenna dwell. after acquisition, cse is updated every 64 symbols. in the event of signal loss after acquisition, cse may go inactive. demodulator description the receiver portion of the baseband processor, performs a/d conversion and demodulation of the spread spectrum signal. it correlates the pn spread symbols, then demodulates the dbpsk, dqpsk, bmbok, or qmbok symbols. the demodulator includes a frequency tracking loop that tracks and removes the carrier frequency offset. in addition it tracks the symbol timing, and differentially decodes (where appropriate) and descrambles the data. the data is output through the rx port to the external processor. the prism baseband processor, hfa3860 uses differential demodulation for the initial acquisition portion of the message processing and then switches to coherent demodulation for the rest of the acquisition and data demodulation. the hfa3860 is designed to achieve rapid settling of the carrier tracking loop during acquisition. rapid phase ?uctuations are handled with a relatively wide loop bandwidth. coherent processing improves the ber performance margin as opposed to differentially coherent processing and is necessary for processing the two higher data rates. the baseband processor uses time invariant correlation to strip the pn spreading and phase processing to demodulate the resulting signals in the header and dbpsk/dqpsk demodulation modes. these operations are illustrated in figure 14 which is an overall block diagram of the receiver processor. in processing the dbpsk header, input samples from the i and q a/d converters are correlated to remove the spreading sequence. the peak position of the correlation pulse is used to determine the symbol timing. the sample stream is decimated to the symbol rate and the phase is corrected for frequency offset prior to psk demodulation. phase errors from the demodulator are fed to the nco through a lead/lag filter to maintain phase lock. the variance of the phase error is used to determine signal quality for acquisition and lock detection. the hfa3860
4- 17 demodulated data is differentially decoded and descrambled before being sent to the header detection section. in the 1 mbps dbpsk mode, data demodulation is performed the same as in header processing. in the 2 mbps dqpsk mode, the demodulator demodulates two bits per symbol and differentially decodes these bit pairs. the bits are then serialized and descrambled prior to being sent to the output. in the mbok modes, the receiver uses a complex multiplier to remove carrier frequency offsets and a bank of serial correlators to detect the modulation. a biggest picker finds the largest correlation in the i and q channels and determines the sign of those correlations. for this to happen, the demodulator must know absolute phase which is determined by referenc ing the data to the last bit of the header. each symbol demodulated determines 1 or 2 nibbles of data. this is then ser ialized and descrambled before passing on to the output. chip tracking in the mbok modes is chip decision directed. carrier tracking is via a lead/lag ?lter using a digital costas phase detector. acquisition description the prism baseband processor uses a dual antenna mode of operation for compensation against multipath interference losses. two antenna acquisition (recommended for indoor use) during the 2 antenna (diversity) mode the two antennas are scanned in order to ?nd the one with the best representation of the signal. this scanning is stopped once a suitable signal is found and the best antenna is selected. a projected worst case time line for the acquisition of a signal in the two antenna case is shown in figure 12. the synchronization part of the preamble is 128 symbols long followed by a 16-bit sfd. the receiver must scan the two antennas to determine if a signal is present on either one and, if so, which has the better signal. the timeline is broken into 16 symbol blocks (dwells) for the scanning process. this length of time is necessary to allow enough integration of the signal to make a good acquisition decision. this worst case time line example assumes that the signal is present on antenna a1 only (a2 is blocked). it further assumes that the signal arrives part way into the first a1 dwell such as to just barely miss detection. the signal and the scanning process are asynchronous and the signal could start anywhere. in this timeline, it is assumed that all 16 symbols are present, but they were missed due to power amplifier ramp up. since a2 has insufficient signal, the first a2 dwell after the start of the preamble also fails detection. the second a1 dwell after signal start is successful and a symbol timing measurement is achieved. meanwhile signal quality and signal frequency measurements are made simultaneous with symbol timing measurements. when the bit sync level, sq1, and phase variance sq2 are above their user programmable thresholds, the signal is declared present for the antenna with the best signal. more details on the signal quality estimates and their programmability are given in the acquisition signal quality parameters section of this document. at the end of each dwell, a decision is made based on the relative values of the signal qualities of the signals on the two antennas. in the example, antenna a1 is the one selected, so the recorded symbol timing and carrier frequency for a1 are used thereafter for the symbol timing and the pll of the nco to begin carrier de-rotation and demodulation. prior to initial acquisition the nco was inactive and dpsk demodulation processing was used. carrier phase measurement are done on a symbol by symbol basis afterward and coherent dpsk demodulation is in effect. after a brief setup time as illustrated on the timeline of figure 12, the signal begins to emerge from the demodulator. it takes 7 more symbols to seed the descrambler before valid data is available. this occurs in time for the sfd to be received. at this time the demodulator is tracking and in the coherent psk demodulation mode it will no longer scan antennas. one antenna acquisition when only one antenna is being used, the user can delete the antenna switch. no register changes are required. acquisition will follow the timeline of figure 12. acquisition signal quality parameters two measures of signal quality are used to determine acquisition. the ?rst method of determining signal presence is to measure the correlator output (or bit sync) amplitude. this measure, however, ?attens out in the range of high ber and is sensitive to signal amplitude. the second measure is phase noise and in most ber scenarios it is a better indication of good signals plus it is insensitive to signal amplitude. the bit sync amplitude and phase noise are integrated over each block of 16 symbols used in acquisition or over blocks of 64 symbols in the data demodulation mode. the bit sync amplitude measurement represents the peak of the correlation out of the pn correlator. figure 13 shows the correlation process. the signal is sampled at twice the chip rate (i.e., 22 msps). the one sample that falls closest to the peak is used for a bit sync amplitude sample for each symbol. this sample is called the on-time sample. high bit sync amplitude means a good signal. the early and late samples are the two adjacent samples and are used for tracking. hfa3860
4- 18 the other signal quality measurement is based on phase noise and that is taken by sampling the correlator output at the correlator peaks. the phase changes due to scrambling are removed by differential demodulation during initial acquisition. then the phase, the phase rate and the phase variance are measured and integrated for 16 symbols. the phase variance is used for the phase noise signal quality measure (sq2). low phase noise means a stronger received signal. the antenna with the best phase noise is chosen when dual antennas are implemented. hfa3860
4- 19 preamble/header crc-16 rssi (14) i in (12) q in (13) v refp (16) v refn (17) antsel (26) (32) cca (35) rxd tx_data scrambler (3) txd processor interface (36) rxclk 11-bit pn at i q i out (48) q out (47) xor differential encoder b(t) b(t-1) latch xor xor chip rate clk mux clk for dqpsk i ch only for dbpsk spreader dpsk modulator timing generator (10, 18, 20) v dd (analog) (7, 21, 29, 42) v dd (digital) (11, 15, 19) gnd (analog) (6, 22, 31, 41) gnd (digital) (4) txclk (5) tx_rdy (2) tx_pe (33) rx_pe (34) md_rdy antsel (27) (24) sclk (25) sd (23) sdi (8) r/ w (9) cs serial control port transmit port receive port (30) mclk (28) reset test 0 (38) test 1 (37) (39) test 2 (40) test 3 (43) test 4 (44) test 5 (45) test 6 (46) test 7 test port test_ck (1) z -1 mclk figure 11. dsss baseband processor, transmit section clock enable logic a sipo b sipo modified walsh gen modified walsh gen b/q mux output mux 11mhz , hi_rate_start, hi_clk tx_pe scrambled data high rate (mbok) modulator sign bit sign bit dif encode init state hfa3860
4- 20 procedure to set acq. signal quality parameters example there are four registers that set the acquisition signal quality thresholds, they are: cr 8, 9, 10, and 11 (rx_sqx_in_acq). each threshold consists of two bytes, high and low that hold a 16-bit number. these two thresholds, bit sync amplitude cr (8 and 9) and phase error cr (10 and 11) are used to determine if the desired signal is present. if the thresholds are set too low, that increases the probability of missing a high signal to noise detection due to being busy processing a false alarm. if they are set too high, that increases the probability of missing a low signal to noise detection. for the bit sync amplitude, high actually means high amplitude while for phase noise high means low noise or high snr. a recommended procedure is to set these thresholds individually optimizing each one of them to the same false alarm rate with no desired signal present. only the background environment should be present, usually additive gaussian white noise (agwn). when programming each threshold, the other threshold is set so that it always indicates that the signal is present. set register cr8 to 00h while trying to determine the value of the phase error signal quality threshold for registers cr 10 and 11. set register cr10 to ffh while trying to determine the value of the bit sync amplitude signal quality threshold for registers 8 and 9. monitor the carrier sense (crs) output (test 6, pin 45) in test mode 1 and adjust the threshold to produce the desired rate of false detections. crs indicates valid initial pn acquisition. after both thresholds are programmed in the device the crs rate is a logic and of both signal qualities rate of occurrence over their respective thresholds and will therefore be much lower than either. pn correlators description there are two types of correlators in the hfa3860 baseband processor. the ?rst is a parallel matched correlator that correlates for the barker sequence used in preamble, header, and psk data modes. this pn correlator is designed to handle bpsk spreading with carrier offsets up to 50ppm and 11 chips per symbol. since the spreading is bpsk, the correlator is implemented with two real correlators, one for the i and one for the q channel. the same barker sequence is always used for both i and q correlators. these correlators are time invariant matched filters otherwise known as parallel correlators. they use one sample per chip for correlation although two samples per chip are processed. the correlator despreads the samples from the chip rate back to the original data rate giving 10.4db processing gain for 11 chips per bit. while despreading the desired signal, the correlator spreads the energy of any non correlating interfering signal. 16 symbols 126 symbol sync sfd just missed det ant1 symb timing detect ant1 check ant2 tx power ramp no sig found ant2 16 symbols 16 symbols 16 symbols 16 symbols 16 symbols 16 symbols 7s 16 symbols ba babab b detect ant1 sfd det start data seed descrambler 7s check ant2 internal set up time verify ant1 2 notes: 3. worst case timing; antenna dwell starts before signal is full strength. 4. time line shown assumes that antenna 2 gets insufficient signal. figure 12. acquisition timeline hfa3860
4- 21 the second form of correlator is the serial correlator bank used for detection of the mbok modulation. there is a bank of eight 8 chip correlators for the i channel and another 8 for the q channel. these correlators integrate over the symbol and are sampled at the symbol rate of 1.375 msps. each bank of correlators is connected to a biggest picker that finds the correlator output with the largest magnitude output. this finding of 1 out of 8 process determines 3 signal bits per correlator bank. the sign of the correlator output determines 1 more bit per bank. thus, each bank of correlators can determine 4 bits at 1.375 msps. this is a rate of 5.5 mbps. only the i correlator bank is used for bmbok. when both correlator banks are used, this becomes twice that rate or 11 mbps. data demodulation and tracking description (dbpsk and dqpsk modes) the signal is demodulated from the correlation peaks tracked by the symbol timing loop (bit sync) as shown in figure 15. the frequency and phase of the signal is corrected from the nco that is driven by the phase locked loop. demodulation of the dpsk data in the early stages of acquisition is done by delay and subtraction of the phase samples. once phase locked loop tracking of the carrier is established, coherent demodulation is enabled for better performance. averaging the phase errors over 16 symbols gives the necessary frequency information for proper nco operation. the signal quality known as sq2 is the variance in this estimate. configuration register 15 sets the search timer for the sfd. this register sets this time-out length in symbols for the receiver. if the time out is reached, and no sfd is found, the receiver resets to the acquisition mode. the suggested value is # preamble symbols + 16. if several transmit preamble lengths are used by various transmitters in a network, the longest value should be used for the receiver settings. data decoder and descrambler description the data decoder that implements the desired dqpsk coding/decoding as shown in table 10. the data is formed into pairs of bits called dibits. the left bit of the pair is the ?rst in time. this coding scheme results from differential coding of the dibits. vector rotation is counterclockwise for a positive phase shift, but can be reversed with bit 5 or 6 of cr2. for dbpsk, the decoding is simple differential decoding. the data scrambler and de-scrambler are self synchronizing circuits. they consist of a 7-bit shift register with feedback of some of the taps of the register. the scrambler is designed to insure smearing of the discrete spectrum lines produced by the pn code. one thing to keep in mind is that both the differential decoding and the descrambling cause error extension. this causes the errors to occur in groups of 4 and 6. this is due to two properties of the processing. first, the differential decoding process causes errors to occur in pairs. when a symbol error is made, it is usually a single bit error even in qpsk mode. when a symbol is in error, the next symbol will also be decoded wrong since the data is encoded in the change from one symbol to the next. thus, two errors are made on two successive symbols. in qpsk mode, these may be next to one another or separated by up to 2 bits. secondly, when the bits are processed by the descrambler, these errors are further extended. the descrambler is a 7-bit shift register with one or more taps exclusive ored with the bit stream. if for example the scrambler polynomial uses 2 taps that are summed with the data, then each error is extended by a factor of three. dqpsk errors can be spaced the same as the tap spacing, so they can be canceled in the descrambler. in this case, two wrongs do make a right, so the observed errors can be in groups of 4 instead of 6. if a single error is made the whole packet is discarded, so the error extension property has no effect on the packet error rate. t0 + 1 symbol correlator correlation peak t0 + 2 symbols t0 correlator output is the result of correlating the pn sequence with the received signal samples at 2x chip rate early on-time late output repeats correlation time figure 13. correlation process table 10. dqpsk data decoder phase shift dibit pattern (d0, d1) d0 is first in time 000 +90 01 +180 11 -90 10 hfa3860
4- 22 descrambling is self synchronizing and is done by a polynomial division using a prescribed polynomial. a shift register holds the last quotient and the output is the exclusive- or of the data and the sum of taps in the shift register. the transmit scrambler taps are programmed by cr 7. hfa3860
4- 23 preamble/header crc-16 detect rssi (14) 3-bit a/d i in (12) q in (13) 6-bit a/d ref 1.75v 0.25v v refp (16) v refn (17) vr3+ vr3- rssi ref 3 3 mf correlator mf correlator symbol clock clear channel assessment/ (32) cca bit sync phase rotate psk demod lead /lag filter nco phase error rx_data descrambler (35) rxd (3) txd processor interface (36) rxclk z -1 xor diff decoder d(t) d(t-1) analog de-spreader/acquisition dpsk demod and afc timing generator 8 8 signal quality and rssi sq and rssi threshold (10, 18, 20) v dd (analog) (7, 21, 29, 42) v dd (digital) (11, 15, 19) gnd (analog) (6, 22, 31, 41) gnd (digital) (4) txclk (5) tx_rdy (2) tx_pe (33) rx_pe signal quality (34) md_rdy antsel (27) (24) sclk (25) sd (23) sdi (8) r/ w (9) cs serial control port transmit port receive port (30) mclk (28) reset test 0 (38) test 1 (37) (39) test 2 (40) test 3 (43) test 4 (44) test 5 (45) test 6 (46) test 7 test port test_ck (1) a/d ref level adj. mag. / phase and timing distrib. signal quality mclk 8 2v (max) (min) 3-bit a/d 11 -bit barker 11 bit barker and sin/cos rom complx multply carrier phase detect nco walsh correl lead /lag filter chip phase detect timing loop symbol decision sign correct, clock enable filter logic piso high rate section phase and freq jam antsel (26) figure 14. dsss baseband processor, receive section hfa3860
4- 24 data demodulation and tracking description (bmbok and qmbok modes) this demodulator handles the m-ary bi-orthogonal keying (mbok) modulation used for the two highest data rates. it is slaved to the low rate processor which it depends on for initial timing and phase tracking information. the high rate section coherently processes the signal, so it needs to have the i and q channels properly oriented and phased. the low rate section acquires the signal, locks up symbol and carrier tracking loops, and determines the data rate to be used for the mpdu data. the demodulator for the mbok modes takes over when the preamble and header have been acquired and processed. on the last bit of the header, the absolute phase of the signal is captured and used as a phase reference for the high rate demodulator as shown in figure 14. the phase and frequency information from the carrier tracking loop in the low rate section is passed to the loop of the high rate section and control of the demodulator is passed to the high rate section. the signal from the a/d converters is carrier frequency and phase corrected by a complex multiplier (mixer) that multiplies the received signal with the output of the numerically controlled oscillator (nco) and sin/cos look up table. this removes the frequency offset and aligns the i and q channels properly for the correlators. the sample rate is decimated to 11 msps for the correlators after the complex multiplier since the data is now synchronous in time. the walsh correlation section consists of a bank of 8 serial correlators on i and 8 on q. each of these correlators is programmed to correlate for its assigned spread function or its inverse. the demodulator knows the symbol timing, so the correlation is integrated over each symbol and sampled and dumped at the end of the symbol. the sampled correlation outputs from each bank are compared to each other in a biggest picker and the chosen one determines 4 bits of the symbol. three bits come from which of the 8 correlators had the largest output and the fourth is determined from the sign of that output. in the 5.5 mbps or binary mode, only the i channel is operated. this demodulates 4 bits per symbol. in the 11 mbps mode, both i and q channels are used and this detects 8 bits per symbol. the outputs are corrected for absolute phase and then serialized for the descrambler. chip tracking is performed on the de-rotated signal samples from the complex multiplier. these are alternately routed into two streams. the end chip samples are the same as those used for the correlators. the mid chip samples should lie on the chip transitions when the tracking is perfect. a chip phase error is generated if the end sign bits bracketing the mid samples are different. the sign of the error is determined by the sign of the end sample after the mid sample. tracking is only measured when there is a chip transition. note that this tracking is mainly effective since there is a positive snr in the chip rate bandwidth. the symbol clock is generated by selecting one 44mhz clock pulse out of every 32 pulses of the sample clock. chip tracking adjusts the sampling in 1/8th chip increments by selecting which edge of the 44mhz clock to use and which pulse. timing adjustments can be made every 32 symbols as needed. carrier tracking is performed in a four phase costas loop. the initial conditions are copied into the loop from the carrier loop in the low rate section. the end samples from above are used for the phase detection. the phase error for the 11 mbps case is derived from isign*q-qsign*i whereas in binary mode, it is simply isign*q. this forms the error term that is integrated in the lead/lag filter for the nco, closing the loop. demodulator performance this section indicates the typical performance measures for a radio design. the performance data below should be used as a guide. in general, the actual performance depends on the application, interference environment, rf/if implementation and radio component selection. overall eb/n0 versus ber performance the prism chip set has been designed to be robust and energy ef?cient in packet mode communications. the demodulator uses coherent processing for data demodulation. the ?gures below show the performance of the baseband processor when used in conjunction with the hsp3726 if limiter and the prism recommended if ?lters. off the shelf test equipment are used for the rf processing. the curves should be used as a guide to assess performance in a complete implementation. factors for carrier phase noise, multipath, and other degradations will need to be considered on an implementation by implementation basis in order to predict the overall performance of each individual system. figure 15 shows the curves for theoretical dbpsk/dqpsk demodulation with coherent demodulation as well as the prism performance measured for dbpsk and dqpsk. the theoretical performance for bpsk and qpsk is the same as shown on the diagram. figure 16 shows the theoretical and actual performance of the mbok modes. the losses in both figures include rf and if radio losses; they do not reflect the hfa3860 losses alone. the hfa3860 baseband processing losses from theoretical are, by themselves, a small percentage of the overall loss. the prism demodulator performs with an implementation loss of less than 3db from theoretical in a awgn environment with low phase noise local oscillators. for the 1 and 2 mbps modes, the observed errors occurred in groups of 4 and 6 errors. this is because of the error extension properties of hfa3860
4- 25 differential decoding and descrambling. for the 5.5 and 11 mbps modes, the errors occur in symbols of 4 or 8 bits each and are further extended by the descrambling. therefore the error patterns are less well defined. clock offset tracking performance the prism baseband processor is designed to accept data clock offsets of up to 25ppm for each end of the link (tx and rx). this effects both the acquisition and the tracking performance of the demodulator. the budget for clock offset error is 0.75db at 50ppm and the performance is shown in figure 17. this ?gure shows that the baseband processor in the high rate modes is better than at low rates in tracking clock offsets. the data for figure 17 and figure 18 was taken with the snr into the receiver set to achieve 1e -5 ber with no offset. then the offset was varied to determine the change in performance. carrier offset frequency performance the correlators used for acquisition for all modes and for demodulation in the 1 and 2 mbps modes are time invariant matched filter correlators otherwise known as parallel correlators. they use two samples per chip and are tapped at every other shift register stage. their performance with carrier frequency offsets is determined by the phase roll rate due to the offset. for an offset of +50ppm (combined for both tx and rx) will cause the carrier to phase roll 22.5 degrees over the length of the correlator. this causes a loss of 0.22db in correlation magnitude which translates directly to eb/n0 performance loss. in the prism chip design, the correlator is not included in the carrier phase locked loop correction, so this loss occurs for both acquisition and data. in the high rate modes, the data demodulation is done with a set of correlators that are included in the carrier tracking loop, so the loss is less. figure 18 shows the loss versus carrier offset taken out to +50ppm (120khz is 50ppm at 2.4ghz). 567891011121314 eb/n0 1.e -02 ber 1.e -03 1.e -04 1.e -05 1.e -06 1.e -07 figure 15. ber vs eb/n0 performance for psk modes ber 2.0 ber 1.0 thy 1,2 figure 16. ber vs eb/n0 performance for mbok modes 14 13 12 11 10 9 8 7 6 5 ber 1.e-03 1.e-04 1.e-05 1.e-06 1.e-07 eb/n0 thy 5.5 thy 11 ber 5.5 ber 11 figure 17. ber vs clock offset -100 -80 -60 -40 -20 0 20 40 60 80 100 1.00e -03 1.00e -04 1.00e -05 1.00e -06 1.00e -07 ber ber 1.0 ber 2.0 ber 5.5 ber 11 clock offset (ppm) hfa3860
4- 26 a default register con?guration the registers in the hfa3860 are addressed with 6-bit numbers where the lower 2 bits of an 8-bit hexadecimal address are left as unused. this results in the addresses being in increments of 4 as shown in the table below. table 11 shows the register values for a default 802.11 configuration with various rate configurations. the data is transmitted as either dbpsk, dqpsk, bmbok, or qmbok depending on the configuration chosen. it is recommended that you start with the simplest configuration (dbpsk) for initial test and verification of the device and/or the radio design. the user can later modify the cr contents to reflect the system and the required performance of each specific application. figure 18. ber vs carrier offset -50 -40 -30 -20 -10 0 10 20 30 40 50 1.00e -04 1.00e -05 1.00e -06 ber ber 1.0 ber 2.0 ber 5.5 ber 11 carrier offset at 2.4ghz (ppm) table 11. control register values for single antenna acquisition configuration register name type register address hex 1/2/5.5/11 mbps cr0 part / version code r 00 01 cr1 i/o polarity r/w 04 00 cr2 tx & rx control r/w 08 14 cr3 a/d_cal_pos register r/w 0c 02 cr4 a/d_cal_neg register r/w 10 ff cr5 cca antenna control r/w 14 04 cr6 preamble length r/w 18 80 cr7 scramble_tap (rx and tx) r/w 1c 48 cr8 rx_sq1_ acq (high) threshold r/w 20 01 cr9 rx-sq1_ acq (low) threshold r/w 24 88 cr10 rx_sq2_ acq (high) threshold r/w 28 00 cr11 rx-sq2_ acq (low) threshold r/w 2c 98 cr12 sq1 cca thresh (high) r/w 30 01 cr13 sq1 cca thresh (low) r/w 34 98 cr14 ed or rssi thresh r/w 38 20 cr15 sfd timer r/w 3c 90 cr16 signal field (bpsk - 11 chip barker sequence) r/w 40 0a cr17 signal field (qpsk - 11 chip barker sequence) r/w 44 14 cr18 signal field (bpsk - mod walsh sequence) r/w 48 37 cr19 signal field (qpsk - mod walsh sequence) r/w 4c 6e cr20 tx signal field r/w 50 00/01/02/03 cr21 tx service field r/w 54 00 cr22 tx length field (high) r/w 58 ff cr23 tx length field (low) r/w 5c ff hfa3860
4- 27 control registers the following tables describe the function of each control register along with the associated bits in each control register. cr24 rx status r 60 x cr25 rx service field status r 64 x cr26 rx length field status (high) r 68 x cr27 rx length field status (low) r 6c x cr28 test bus address r/w 70 00 cr29 test bus monitor r 74 x cr30 test register 1 r/w 78 00 cr31 test register 2 r/w 7c 02 table 11. control register values for single antenna acquisition (continued) configuration register name type register address hex 1/2/5.5/11 mbps configuration register 0 address (0h) part/version code bit 7:4 part code 0 = hfa3860 bit 3:0 version code 1 = first version configuration register 1 address (04h) i/o polarity this register is used to define the phase of clocks and other interface signals. 00h is normal setting. bit 7 this controls the phase of the rx_clk output logic 1 = invert clk logic 0 = non-inverted clk bit 6 this control bit selects the active level of the md_rdy output pin 34. logic 1 = md_rdy is active 0 logic 0 = md_rdy is active 1 bit 5 this control bit selects the active level of the clear channel assessment (cca) output pin 32. logic 1 = cca active 1 logic 0 = cca active 0 bit 4 this control bit selects the active level of the energy detect (ed) output which is an output pin at the test port, pin 44 . logic 1 = ed active 0 logic 0 = ed active 1 bit 3 this control bit selects the active level of the carrier sense (crs) output pin which is an output pin at the test port, p in 45. logic 1 = crs active 0 logic 0 = crs active 1 bit 2 this control bit selects the active level of the transmit enable (tx_pe) input pin 2. logic 1 = tx_pe active 0 logic 0 = tx_pe active 1 bit 1 this control bit selects the phase of the transmit output clock (txclk) pin 4. logic 1 = inverted txclk logic 0 = non-inverted txclk bit 0 this control bit selects the active level of the transmit ready (tx_rdy) output pin 5. logic 1 = tx_rdy active 0 logic 0 = tx_rdy active 1 hfa3860
4- 28 configuration register 2 address (08h) tx and rx control write to control, read to verify control, setup while tx_pe and rx_pe are low bit 7 mclk control. 0 = 44mhz all signal modes supported. 1 = 22mhz 1 and 2 mbps, b/qpsk 11 chip sequence mode only. reduced power mode. bit 6 tx rotation 0 = normal 1 = invert q out bit 5 rx rotation 0 = normal 1 = invert q in bit4 a/d calibration 0 = a/d_cal off 1 = a/d_cal on bit 3 a/d calibration control (only valid if a/d calibration is on). 0 = a/d calibration only while in receive tracking mode (a/d calibration set on signals only). 1 = a/d calibration while receive rx_pe is active (in this mode, the a/d calibration will be set primarily on noise). bit 2 this bit enables/disables energy detect (ed) for the cca function. 0 = ed off 1 = ed on bit 1 md_rdy start. sets where md_rdy will become active. 0 = after sfd detect (normal). this allows the header fields to be enveloped by md_rdy. 1 = after header crc verify and start of mpdu. header data can be read from configuration registers. bit 0 tx and rx clock 0 = enable gated clocks (normal). rx clock will come on to clock out header ?elds, go off during crc and come back on for mpdu data. header rate is 1mhz, data rate is variable. txclk comes on after txrdy active. 1 = clocks start as soon as modem starts tracking and remain on until either header checks fail or until rx_ pe goes back low. this is only usable in the 1 and 2 mbps modes. txclk comes on after tx_pe active. configuration register 3 address (0ch) a/d cal pos bits 0 - 7 this 8-bit control register contains a binary value used for positive increment for the level adjusting circuit of the a/d reference. the larger the step the faster the a/d calibration settles. configuration register 4 address (10h) a/d cal neg bits 0 - 7 this 8-bit control register contains a binary value used for the negative increment for the level adjusting circuit of the a/d reference. the number is programmed as 256 - the value wanted since it is a negative number. configuration register 5 address (14h) cca antenna control bits 7:3 r/w, but not used internally bit 2 reserved. must be set to a 1. bits 1:0 cca antenna mode. defines the antenna to be used at the start of acquisition for cca checking and for subsequent transmission. tx antenna is always the same as used to check cca. controls antenna selection via the ant_sel pin. 00 = use last receive antenna for cca checking and tx. acquisition starts on the antenna which had a valid header on last reception. 01 = illegal state - unknown behavior 10 = use antenna b for cca and tx. antsel = 0 11 = use antenna a for cca and tx. antsel = 1 configuration register 6 address (18h) preamble length bits 0 - 7 this register contains the count for the preamble length counter. setup while tx_pe is low. for ieee 802.11 use 80h. for other than ieee 802.11 applications, in general increasing the preamble length will improve low signal to noise acquisition performance at the cost of greater link overhead. for dual receive antenna operation, the minimum suggested value is 128d = 80h. for single receive antenna operation, the minimum suggested value is 80d = 50h. these suggested values includ e a 2 symbol tx power amplifier ramp up. if you program 128 you get 130. hfa3860
4- 29 configuration register 7 address (1ch) scrambler taps bit 7 0 = normal, rx_pe enables/disables the internal receive clock. i = internal receive clock is always enabled. bits 6:0 this register is used to con?gure the transmit scrambler with a 7-bit polynomial tap con?guration. the transmit scrambler is a 7-bit shift register, with 7 con?gurable taps. a logic 1 is the respective bit position enables that particular tap. the example below illustrates the register con?guration for the polynomial f(x) = 1 + x -4 +x -7 . each clock is a shift left. lsb bits (6:0) 6 5 4 3 2 1 0 term x -7 x -6 x -5 x -4 x -3 x -2 x -1 scrambler taps f(x) = 1 + x -4 +x -7 1 0 0 1 0 0 0 configuration register 8 address (20h) sq1 acq threshold (high) bits 0 - 7 this control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for acquisition. this register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude signal quality measurements made during acquisition at each antenna dwell. this threshold comparison is added with the sq2 threshold in registers 10 and 11 for acquisition. a lower value on this threshold will increase the probability of detection and the probability of false alarm. configuration register 9 address (24h) sq1 acq threshold (low) bits 0 - 7 this control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for acquisition. this register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude signal quality measurement made during acquisition at each antenna dwell. configuration register 10 address (28h) sq2 acq threshold (high) bits 0 - 7 this control register contains the upper byte bits (8-15) of the carrier phase variance threshold used for acquisition. this register combined with the lower byte represents a 16-bit threshold value for carrier phase variance measurement made during acquisition at each antenna dwell and is based on the choice of the best antenna. this threshold is used with the bit sync threshold in registers 8 and 9 to declare acquisition. a higher value in this threshold will increase the probability of acquisition and false alarm. configuration register 11 address (2ch) sq2 acq threshold (low) bits 0 - 7 this control register contains the lower byte bits (0-7) of the carrier phase variance threshold used for acquisition . configuration register 12 address (30h) sq1 cca threshold (high) bits 0 - 7 this control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for cca estimation. this register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude signal quality measurement made during acquisition on cca antenna dwell. a lower value on this threshold will increase the probability of detection and the probability of false alarm. set the threshold according to instructions in the text. configuration register 13 address (34h) sq1 cca threshold (low) bits 0 - 7 this control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for cca. this register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude signal quality measurement made during acquisition on cca antenna dwell. hfa3860
4- 30 configuration register 14 address (38h) ed or rssi threshold bit 7:6 r/w, but not used internally bits 5:0 this register contains the value for the rssi threshold for measuring and generating energy detect (ed). when the rssi exceeds the threshold ed is declared. ed indicates the presence of energy in the channel. to disable the ed signal so that it has no affect on the cca logic, the threshold must be set to a 3fh (all ones). msb lsb bits (0:5) 5 4 3 2 1 0 0 0 0 0 0 0 00h (min) rssi_stat 1 1 1 1 1 1 3fh (max) configuration register 15 address (3ch) sfd timer bits 7:0 this register is programmed with an 8-bit value which represents the length of time for the demodulator to search for a sfd in a receive header. each bit increment represents 1 symbol period. failure to ?nd the sfd will result in a return to acquisition mode. configuration register 16 address (40h) signal field dbpsk bits 7:0 this register contains an 8-bit value de?ning the data packet modulation as dbpsk. this value will be a oah for 802.11, and is used in the transmitted signalling field of the header. this value will also be used for detecting the modulation type on the received header. configuration register 17 address (44h) signal field dqpsk bits 7:0 this register contains the 8-bit value de?ning the data packet modulation as dqpsk. this value will be a 14h for full protocol operation at a data rate of 2 mbps and is used in the transmitted signalling field of the header. this value will also be used for detecting the modulation type on the received header. configuration register 18 address (48h) signal field bmbok bits 7:0 this register contains the 8-bit value de?ning the data packet modulation as bmbok. this value will be a 37h for operation at a data rate of 5.5 mbps and is used in the transmitted signalling field of the header. this value will also be used for detecting the modulation type on the received header. configuration register 19 address (4ch) signal field qmbok bits 7:0 this register contains the 8-bit value de?ning the data packet modulation as qmbok. this value will be a 6eh for operation at a data rate of 11 mbps and is used in the transmitted signalling field of the header. this value will also be used for detecting the modulation type on the received header. configuration register 20 address (50h) tx signal field bits 7:2 r/w, but not used internally bits 1:0 tx data rate. must be set at least 2 m s before needed in tx frame. this selects tx signal ?eld code from the registers above. 00 = dbpsk - 11 chip sequence (1 mbps) 01 = dqpsk - 11 chip sequence (2 mbps) 10 = bmbok - modified 8 chip walsh sequence (5.5 mbps) 11 = qmbok - modified 8 chip walsh sequence (11 mbps) configuration register 21 address (54h) tx service field bits 7:0 this 8-bit register is programmed with the 8-bit value of the service ?eld to be transmitted in the header. this ?eld is reserved for future use and should always be set to 00h. hfa3860
4- 31 configuration register 22 address (58h) tx length field (high) bits 7:0 this 8-bit register contains the higher byte (bits 8-15) of the transmit length field described in the header. this byte combined with the lower byte indicates the number of bits to be transmitted in the data packet. configuration register 23 address (5ch) tx length field (low) bits 7:0 this 8-bit register contains the lower byte (bits 0-7) of the transmit length field described in the header. this byte combined with the higher byte indicates the number of bits to be transmitted in the data packet. configuration register 24 address (60h) rx status this read only register is provided for macs that cant process the header fields from the rxd port. bits 7:6 rx signal field detected 00 = dbpsk - 11 chip sequence (1 mbps) 01 = dqpsk - 11 chip sequence (2 mbps) 10 = bmbok - modified 8 chip walsh sequence (5.5 mbps) 11 = qmbok - modified 8 chip walsh sequence (11 mbps) bit 5 search/acquisition status (set to 0 when rx_pe is inactive) 0 = searching 1 = carrier acquired bit 4 sfd search status (set to 0 when rx_pe is inactive) 0 = searching 1 = sfd found bit 3 signal field valid (set to 0 when rx_pe is inactive) signal field must be one of the 4 field values in cr 16 to cr19 0 = not valid 1 = valid bit 2 valid header crc (set to 0 when rx_pe is inactive) 0 = not valid 1 = valid bit 1 antenna received on. indicates which antenna the receiver was on when the last valid crc occurred. 0 = antenna b 1 = antenna a bit 0 always 0 configuration register 25 address (64h) rx service field status bits 7:0 this register contains the detected received 8-bit value of the service field for the header. this ?eld is reserved for future use. it should be the value programmed into register 21 of the transmitter. configuration register 26 address (68h) rx length field status (high) bits 7:0 this register contains the detected higher byte (bits 8-15) of the received length field contained in the header. this byte combined with the lower byte indicates the number of transmitted bits in the data packet. configuration register address 27 (6ch) rx length field status (low) bits 7:0 this register contains the detected lower byte of the received length field contained in the header. this byte combined with the upper byte indicates the number of transmitted bits in the data packet. hfa3860
4- 32 configuration register 28 address (70h) test bus address supplies address for test pin outputs and test bus monitor register bits 7:0 test bus address = 00h quiet test bus test 7:0 = 00 test_clk = 0 bits 7:0 test bus address = 01h rx acquisition monitor these bits sequentially go high as the signal is input. transitions are aligned to chip boundaries. bits are reset after last chip of message. test 7 = a/dcal (full scale) test 6 = crs, carrier sense test 5 = ed, energy detect comparator output test 4 = track, indicates start of tracking and start of sfd time-out test 3 = sfd detect, variable time after track start test 2 = signal field ready, ~ 8 m s after sfd detect test 1 = length field ready, ~ 32 m s after sfd detect test 0 = header crc valid, ~ 48 m s after sfd detect test_clk = initial detect bits 7:0 test bus address = 02h tx field monitor . these bits sequentially go high as the signal is output. transitions are aligned to chip boundaries. bits are reset after last chip of valid message. test 7 = a/dcal (full scale) test 6 = txpe internal, inactive edge of pad txpe delayed test 5 = preamble start test 4 = sfd start test 3 = signal field start test 2 = length field start test 1 = header crc start test 0 = mpdu start test_clk = iqmark, identifies symbol boundaries on iout and qout bits 7:0 test bus address = 03h rssi monitor test 7 = cse latched by rssi pulse test 6 = cse, carrier sense early (sqi cca only) test 5:0 = rssi(5:), bit 5 is msb, straight binary (000000 = min, 11111 = max) test_clk = rssi a/d clk, sample rssi(5:0) on last rising edge bits 7:0 test bus address = 04h sq1 monitor test 7:0 = sq1 (7:0) test_clk = pulse after sq is valid bits 7:0 test bus address = 05h sq2 monitor test 7:0 = sq2 (7:0) test_clk = pulse after sq is valid bits 7:0 test bus address = 06h correlator lo rate test 7:0 = correlator magnitude lo rate only test_clk = sample clk bits 7:0 test bus address = 07h freq test lo rate test 7:0 = freq reg lo rate (18:11) test_clk = subsampleclk (symbol clock) bits 7:0 test bus address = 08h phase test lo rate test 7:0 = phase reg lo rate (7:0) test_clk = subsampleclk (symbol clock) bits 7:0 test bus address = 09h nco test lo rate test 7:0 = nco reg lo rate (15:8) test_clk = subsampleclk (symbol clock) hfa3860
4- 33 bits 7:0 test bus address = 0ah bit sync accum lo rate test 7:0 = bit sync accumulator (7:0) test_clk = sample clk bits 7:0 test bus address = 0bh test pn gen., factory test only test 7:0 +test_clk = top 9 bits of pn generator used for fault tests. bits 7:0 test bus address = 0ch a/d cal test mode test 7 = a/d cal (full scale) test 6 = ed, energy detect comparator output test 5 = a/d_cal disable test(4:0) = a/d_cal(4:0) test_clk =a/d_cal clk bits 7:0 test bus address = 0dh correlator i high rate, tests the mbok i correlator output. test 7:0 = correlator i hi rate (8:1) test_clk = sample clk bits 7:0 test bus address = 0eh correlator q high rate, tests the mbok q correlator output. test 7:0 = correlator q hi rate (8:1) test_clk = sample clk bits 7:0 test bus address = 0fh chip error accumulator, test 7:0 = chip error accumulator (14:7) test_clk = 0 bits 7:0 test bus address = 10h nco test hi rate, tests the nco in the high rate tracking section. test 7:0 = nco accum (19:12) test_clk = sample clk bits 7:0 test bus address = 11h freq test hi rate, tests the nco lag accumulator in the high rate tracking section. test 7:0 = lag accum (18:11) test_clk = sample clk bits 7:0 test bus address = 12h carrier phase error hi rate test 7:0 = carrier phase error (6,6:0) test_clk = sample clk bits 7:0 test bus address = 13h i_rot hi rate, tests the i channel phase rotation error signal. test 7:0 = i_rot (5,5,5:0) test_clk = sample clk bits 7:0 test bus address = 14h q_rot hi rate test 7:0 = q_rot (5,5,5:0) test_clk = sample clk bits 7:0 test bus address = 15h i_a/d, q_a/d, tests the i and q channel 3-bit a/d converters. test 7:6 = 0 test 5:3 = i_a/d (2:0) test 2:0 = q_a/d (2:0) test_clk = sample clk bits 7:0 test bus address = 16h xor hi rate, factory test only test 7:0 + test_clk = 9 bits of registered xor test data from the high rate logic. configuration register 28 address (70h) test bus address (continued) supplies address for test pin outputs and test bus monitor register hfa3860
4- 34 bits 7:0 test bus address = 17h xor fast, factory test only test 7:0 + test_clk = 9 bits of registered xor test data from the low rate logic. bits 7:0 test bus address = 18h timing test, tests the receiver timing. test 7 = jmpclk test 6 = jmpcnt test 5 = subsampleclk test 4:0 = mastertim(4:0) test_clk = sample clk bits 7:0 test bus address = 19h a/d cal accum lo, tests the lo bits of the a/d cal accumulator. test 7:0+testclk = a/d cal accum (8:0) bits 7:0 test bus address = 1ah a/d cal accum hi, tests the hi bits of the a/d cal accumulator. test 7:0+testclk = a/d cal accum (17:9) bits 7:0 test bus address = 1bh freq accum lo, tests the frequency accumulator of the low rate section. test 7:0+testclk = freq accum (15:7) bits 7:0 test bus address = 1ch slow xor, factory test test 7:0 = 8 bits of registered xor test data from the low rate logic test_clk = subsampleclk bits 7:0 test bus address = 1dh sq2 monitor hi test 7:0 = sq2 (15:8) test_clk = pulse after sq is valid bits 7:0 test bus address = 1eh to 1fh reserved test 7:0 + testclk = 0 configuration register 28 address (70h) test bus address (continued) supplies address for test pin outputs and test bus monitor register configuration register 29 address (74h) test bus monitor bits 7:0 maps test bus pins 7:0 to read only value 7:0 when test bus address is supplied by cr 28 configuration register 30 address (78h) test register 1 bits 7 pn generator for fault test 0 = normal 1 = enabled bit 6 change mux control in subsample path 0 = normal 1 = changed bit 5 hr demod xor to test bus enable 0 = normal 1 = enabled bit 4 random address to test bus 0 = normal 1 = enabled bit 3 faster cal 0 = normal 1 = enabled when enabled, the 1khz clock used to update the a/d cal bits is increased to 22khz. hfa3860
4- 35 bit 2 a/d cal test mode 0 = normal 1 = enabled when enabled, the 5 a/d cal bits come from cr3<4:0> to allow direct control. bit 1 a/d test mode 0 = normal 1 = enabled when enabled, this bit causes all 12 bits of a/d outputs (6 rssi, 3 i, 3 q) to be directly output on pins of the hfa3860. modem is non-functional. bit 0 loop back 0 = normal 1 = enabled when enabled, this bit routes the i and q outputs to the i and q inputs of the modem. the 3-bit i&q a/ds are bypassed. configuration register 30 address (78h) test register 1 (continued) configuration register 31 address (7ch) test register 2 bits 7:2 r/w but not currently used internally, should be set to zero to ensure compatibility with future revisions. bit 1 disable control 0 = ed disabled 19 m s after rxpe active 1 = ed runs continuously, updates every ant dwell bit 0 cca type select 0 = rawcca, updates every ant dwell 1 = snapshot (latched) cca hfa3860
4- 36 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0v input, output or i/o voltage . . . . . . . . . . . . gnd -0.5v to v cc +0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 2 operating conditions voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.70v to +3.60v temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 5) q ja ( o c/w) tqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (lead tips only) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33,000 gates caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 5. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations v cc = 3.0v to 3.3v 10%, t a = -40 o c to 85 o c parameter symbol test conditions min typ max units power supply current i ccop v cc = 3.6v, clk frequency 44mhz (notes 6, 7) -3040ma standby power supply current i ccsb v cc = max, outputs not loaded - 0.5 1 ma input leakage current i i v cc = max, input = 0v or v cc -10 1 10 m a output leakage current i o v cc = max, input = 0v or v cc -10 1 10 m a logical one input voltage v ih v cc = min, max 0.7 v cc --v logical zero input voltage v il v cc = min, max - - v cc /3 v logical one output voltage v oh i oh = -1ma, v cc = min v cc -0.2 - - v logical zero output voltage v ol i ol = 2ma, v cc = min - .2 0.2 v input capacitance c in clk frequency 1mhz. all measurements referenced to gnd. t a = 25 o c, note 7 - 5 10 pf output capacitance c out - 5 10 pf notes: 6. output load 30pf. 7. not tested, but characterized at initial design and at major process/design changes. ac electrical speci?cations v cc = 3.0v to 3.3v 10%, t a = -40 o c to 85 o c (note 8) parameter symbol mclk = 44mhz units min max mclk period t cp 22 - ns mclk duty cycle 43/57 57/43 % rise/fall (all outputs) - 10 ns (notes 9, 10) tx_pe to iout/qout (1st valid chip) t d1 2.18 2.3 m s (notes 9, 11) tx_pe inactive width t tlp 2.22 - m s (notes 9, 12) tx_clk width hi or low t tcd 40 - ns tx_rdy active to 1st tx_clk hi t rc 260 - ns setup txd to tx_clk hi t tds 30 - ns hold txd to tx_clk hi t tdh 0-ns tx_clk to tx_pe inactive (1 mbps) t peh 0 965 ns (notes 9, 22) tx_clk to tx_pe inactive (2 mbps) t peh 0 420 ns (notes 9, 22) tx_clk to tx_pe inactive (5.5 mbps) t peh 0 160 ns (notes 9, 22) tx_clk to tx_pe inactive (11 mbps) t peh 0 65 ns (notes 9, 22) tx_rdy inactive to last chip of mpdu out t ri -20 20 ns hfa3860
4- 37 txd modulation extension t me 2- m s (notes 9, 13) rx_pe inactive width t rlp 70 - ns (notes 9, 14) rx_clk period (11 mbps mode) t rcp 77 - ns rx_clk width hi or low (11 mbps mode) t rcd 31 - ns rx_clk to rxd t rdd 20 60 ns md_rdy to 1st rx_clk t rd1 940 - ns (notes 9, 17) rxd to 1st rx_clk t rd1 940 - ns setup rxd to rx_clk t rds 31 - ns rx_clk to rx_pe inactive (1 mbps) t reh 0 925 ns (notes 9, 15) rx_clk to rx_pe inactive (2 mbps) t reh 0 380 ns (notes 9, 15) rx_clk to rx_pe inactive (5.5 mbps) t reh 0 140 ns (notes 9, 15) rx_clk to rx_pe inactive (11 mbps) t reh 0 50 ns (notes 9, 15) rx_pe inactive to md_rdy inactive t rd2 5 30 ns (note 16) last chip of sfd in to md_rdy active t rd3 2.77 2.86 m s (notes 9, 17) rx delay 2.77 2.86 m s (notes 9, 18) reset width active t rpw 50 - ns (notes 9, 19) rx_pe to cca valid t cca -16 m s (notes 9, 20) rx_pe to rssi valid t cca -16 m s (notes 9, 20) antsel lead time 820 - ns (notes 9, 21) sclk clock period t scp 90 - ns sclk width hi or low t scw 20 - ns setup to sclk + edge (sd, sdi, r/w, cs) t scs 30 - ns hold time from sclk + edge (sd, sdi, r/w, cs) t sch 0-ns sd out delay from sclk + edge t scd -30ns sd out enable/disable from r/w t sced - 15 ns (note 9) test 0-7, cca, antsel, test_ck from mclk t d2 -50ns notes: 8. ac tests performed with c l = 40pf, i ol = 2ma, and i oh = -1ma. input reference level all inputs 1.5v. test v ih =v cc ,v il =0v; v oh =v ol =v cc /2. 9. not tested, but characterized at initial design and at major process/design changes. 10. measured from v il to v ih . 11. iout/qout are modulated before first valid chip of preamble is output to provide ramp up time for rf/if circuits. 12. tx_pe must be inactive before going active to generate a new packet. 13. iout/qout are modulated after last chip of valid data to provide ramp down time for rf/if circuits. 14. rx_pe must be inactive at least 3 mclks before going active to start a new cca or acquisition. 15. rx_pe active to inactive delay to prevent next rx_clk. 16. assumes rx_pe inactive after last rx_clk. 17. md_rdy programmed to go active after sfd detect. (measured from i in , q in ). 18. md_rdy programmed to go active at mpdu start. measured from first chip of first mpdu symbol at i in , q in to md_rdy active. 19. minimum time to insure reset. reset must be followed by an rx_pe pulse to insure proper operation. this pulse should not be used for first receive or acquisition. 20. cca and rssi are measured once during the first 16 us interval following rx_pe going active. rx_pe must be pulsed to initiate a new measurement. rssi may be read via serial port or from test bus. 21. antsel is switched in diversity mode before acquisition cycle to compensate for delays in if circuits. the correlators will be 100x(820ns - tdrfns)/990 ns% full of new data at the beginning of bit sync accumulation. tdrfns is the settling time of the rf circuits afte r antsel switches. 22. delay from txclk to inactive edge of txpe to prevent next txclk. because txpe asynchronously stops txclk, txpe going inactive within 40ns of txclk will cause txclk minimum hi time to be less than 40ns. ac electrical speci?cations v cc = 3.0v to 3.3v 10%, t a = -40 o c to 85 o c (note 8) (continued) parameter symbol mclk = 44mhz units min max hfa3860
4- 38 test circuit i and q a/d ac electrical speci?cations (note 9) parameter min typ max units full scale input voltage (v p-p ) 0.25 0.50 1.0 v input bandwidth (-0.5db) - 20 - mhz input capacitance - 5 - pf input impedance (dc) 5 - - k w fs (sampling frequency) - - 22 mhz rssi a/d electrical speci?cations (note 9) parameter min typ max units full scale input voltage (v p-p ) - - 1.15 v input bandwidth (0.5db) 1mhz - - mhz input capacitance (dc) - 7pf - pf input impedance 1m - - m w notes: 23. includes stray and jig capacitance. 24. switch s1 open for i ccsb and i ccop . figure 19. test load circuit equivalent circuit c l ioh 1.5v iol dut s 1 (note 24) (note 23) figure 20. serial control port signal timing t scp t scs t sch t scd t sced t sced sclk sdi, r/ w, sd, cs sd (as output) r/ w sd t scw t scw hfa3860
4- 39 figure 21. tx port signal timing note: rxd, md_rdy is output two mclk after rxclk rising to provide hold time. rssi output on test (5:0). figure 22. rx port signal timing note: delays will occur from rising or falling edige of mclk if cr2 bit 7 is set to a 1. figure 23. miscellaneous signal timing t tlp t peh t ri t tcd t tcd t rc t d1 t tds t tdh tx_pe i out , q out txrdy tx_clk txd t me t rlp t rd3 t reh t rd2 rx_pe i in , q in md_rdy rx_clk rxd cca, rssi t rcp t rcd t rcd t rdd t rd1 t rds t cca reset mclk t cp t rpw t d2 mclk test 0-7, cca, antsel, test_ck hfa3860
4- 40 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hfa3860

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